There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors.
FIG. 1 shows a conventional imager 200 that includes an array of pixels 230 and a timing and control circuit or controller 232 which provides timing and control signals to control the reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M times N pixels, with the size of the array 230 depending on the particular application. The imager is read out a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on column lines 170 (FIG. 2) to a readout circuit 242 as conventionally known. Referring back to FIG. 1, the pixel signal read from each of the columns can then be read out sequentially using a column addressing circuit 244. Differential pixel signals corresponding to the read out reset signal (Vrst) and integrated charge signal (Vsig) are provided as respective outputs Vout1, Vout2 of the readout circuit 242.
FIG. 2 more clearly shows the rows and columns 349 of pixel array 230 and the associated readout circuit 242. Each column 349 includes multiple rows of pixels 350. The readout circuit 242 includes sample and hold circuitry 351 for storing the pixel reset (Vrst) and integrated charge signals (Vsig). Signals from the pixels 350 in a particular column 349 can be read out through a column line 170 to the sample and hold circuit 351 associated with that column. Typically, Vrst is stored in capacitor c_rst and Vsig is stored in capacitor c_sig in the sample and hold circuit 351. The gain of the sample and hold circuit 351 is a function of a biasing current Iln connected to the column line 170.
Signals stored in the readout circuit 242 can be read out sequentially column-by-column to an output stage 354, which is common to the entire array of pixels 330. Output stage 359 provides two output signals Vout1, Vout2 that correspond to the Vsig, Vrst signals, respectively. The analog output signals Vout1, Vout2 can then be sent, for example, to a differential analog circuit, which subtracts the reset and integrated charge signals and sends the subtracted signal to an analog-to-digital converter (ADC); alternatively, the reset and integrated charge signals can be supplied directly to the analog-to-digital converter.
During manufacture, each imaging pixel array is usually tested individually. Tests detect defective pixel circuits, pixel signal level, and other array attributes, and the information is stored based on lot and individual device identification numbers. The information developed during testing can be utilized to enhance the operation of the device by, for example, compensating for defective pixels, differing pixel signal levels, and other tested pixel attributes.
Because variances occur during manufacturing, the capacitance values of capacitors c_rst and c_sig will be different, ideally only slightly different. However, it is not easy or cheap to test the capacitance value of each capacitor c_rst, c_sig and then modify the capacitors to have the same capacitance value. Thus, capacitors c_rst and c_sig of each sample and hold circuit 351 will add a different amount of column-wise fixed pattern noise to the readout process.
Similarly, the bias current Iln will vary from column to column. Although the difference may not be large, nonetheless, the different Iln current values will add different amounts of gain during read out of each sample and hold circuit 351. Thus, the bias current Iln of each sample and hold circuit 351 will add a different amount of column-wise fixed pattern noise to the relevant process.
The human eye is sensitive to column-wise noise, which may manifest as a column in an image being different from surrounding columns of the image. Therefore, it is desirable to modify the imager to reduce the visual obviousness of column-wise fixed pattern noise